Design Integrity Status Report
------------------------------

Report Written:     08:08 Friday, September 27, 2024
Project Path:       V:\CTLAB\PCB\FPGA-ISRAM\FPGA.prj
Design Path:        V:\CTLAB\PCB\FPGA-ISRAM\FPGA.pcb
Design Title:       
Created:            14.12.2006 13:34:15
Last Saved:         27.09.2024 08:07:27
Editing Time:       32013 min
Units:              thou (precision 2)


Checking integrity of Schematic and Pcb designs in project "FPGA"
=================================================================


Warning: Project has more than one version of Component "CP1" ("FPGA-RTC.sch" & "FPGA.sch"). At least one should be reloaded otherwise results may be incorrect.


End Of Report.
